一个LVTSCR并联PMOS的高维持电压ESD防护器件(英文)  

A PMOS multipled LVTSCR device for ESD protection with a higher holding voltage

作　　者：蒋同全 汪洋[1,2] 黄薇[1,2] 罗启元[1,2] 金湘亮[1,2] 

机构地区：[1]湘潭大学材料与光电物理学院,湖南湘潭411105 [2]湘潭大学微光电与系统集成湖南省工程实验室,湖南湘潭411105

出　　处：《太赫兹科学与电子信息学报》2014年第2期315-320,共6页Journal of Terahertz Science and Electronic Information Technology

基　　金：supported by the National Natural Science Foundation of China(Grant No.61274043);by the State Key Program of National Natural Science of China(Grant No.61233010);the Key Project of Chinese Ministry of Education(Grant No.212125);Creative Project in Xiangtan University

摘　　要：为了在5 V片上输入输出端进行静电放电(ESD)防护,提出了一种新型的LVTSCR结构。使用Silvaco 2D TCAD软件对此器件进行包含电学及热学特性的仿真。此新型器件交换了LVTSCR中N-Well的N+、P+掺杂区并引入了一个类PMOS结构用来在LVTSCR工作前释放ESD电流。器件仿真结果显示,与LVTSCR相比,该器件获得了更高的维持电压(10.51 V),以及更高的开启速度(1.05×10-10 s),同时触发电压仅仅从12.45 V增加到15.35 V。并且,如果加入的PMOS结构选择与NMOS相同的沟道长度,器件不会引起热失效问题。A novel LVTSCR structure for 5 V on-chip protection against Electrostatic Discharge(ESD) stress at input or output pads is presented. Silvaco 2D TCAD software is used to simulate the device including electrical and thermal characteristics. The new device exchanges the diffusion region of N+ and P+ in N-WELL and introduces a PMOS-like structure to discharge ESD current before Low Voltage Triggering SCR(LVTSCR) starting to work. And the device simulation results show that it obtains a higher holding voltage(10.51 V) and a faster turn on speed(1.05×10-10 s) compared with LVTSCR, with the triggering voltage only increasing slightly from 12.45 V to 15.35 V. Also, in order to make sure that the PMOS structure will trigger first and will not cause thermal breakdown problem, nearly the same channel length as NMOS should be chosen for PMOS structure.

关 键 词：静电放电 低压触发可控硅器件 PMOS触发 Silvaco软件 

分 类 号：TN386[电子电信—物理电子学]