高速时钟电路的信号完整性设计  

Signal Integrity of High - speed Design

作　　者：吕霆[1] 祝亮[1] 

机构地区：[1]中国电子科技集团公司第54研究所,河北石家庄050081

出　　处：《电子工艺技术》2004年第1期39-41,共3页Electronics Process Technology

摘　　要：电子技术的发展日新月异,高速数字电路(即高时钟频率及快速边沿)的设计成为主流,给PCB设计带来许多问题和挑战。阐述了高速时钟电路设计过程中遇到的信号完整性问题,同时也给出了这些问题的解决方法。With the development of electronic science technolgy, throughout the PCB design process, the designers must address high - speed issues of increasing density, complexity, and faster edge rates. And the designers will face series of problems, such as SI, EMI, cross talk, overshoot and undershoot, and so on. introduce some technique collected by author about solving those problems.

关 键 词：高速设计 信号完整性 解决方法 高速数字电路 高速时钟电路 

分 类 号：TN79[电子电信—电路与系统]