基于内插与积分清除滤波的相干DLL性能分析  

Performance Analysis ofCoherent Delay-Locked Loop Based onInterpolation and Integrate/Dump Filter

作　　者：李科祥[1] 宋国文[2] 

机构地区：[1]信息工程大学通信工程系,郑州450002 [2]西南电子电信技术研究所上海分所,上海20043

出　　处：《电子与信息学报》2004年第1期27-34,共8页Journal of Electronics & Information Technology

基　　金：863-371-03-01-10-99项目资助课题

摘　　要：提出一种基于内插与积分清除滤波的相干延迟锁定环(CDLL),用于直接序列码分多址(DS-CDMA)系统的伪随机码跟踪,并对其进行了性能分析。通过将该CDLL定时调整过程等效为一带反射壁的齐次马尔可夫链,导出了AWGN与多用户环境下定时误调整概率、定时均方根抖动、失锁概率以及平均失锁时间(MTLL)的表达式,最后给出了数值仿真结果,分析并指出本文的分析结果同样适应于单径衰落环境。该锁定环在WCDMA基站系统和移动终端的开发中得到应用。A Coherent Delay-Locked Loop(CDLL) is proposed based on interpolation and integrate/dump filter for PN code tracking in DS-CDMA systems. The performance of the CDLL is investigated under AWGN and multi-user environments, and closed-form expressions for the timing adjustment error probability, steady-state timing squared root error, probability and Mean Time to Lose Lock (MTLL) are derived by employing appropriate Markov chain models. Finally, sonic numerical results are presented and analysis shows that those results also perform well in single path fading environment. The delay-locked loop is applied to the development of WCDMA BTS and WCDMA MT.

关 键 词：CDMA系统 直接序列码分多址 DLL性能 相干延迟锁定环 内插滤波 积分清除滤波 延迟锁定环 

分 类 号：TN914.53[电子电信—通信与信息系统]