基于互连的一种FPGA最优功耗延时积设计  

New design method for the optimal energy delay product ofFPGA based on the interconnect

作　　者：马群刚[1] 杨银堂[1] 李跃进[1] 

机构地区：[1]西安电子科技大学微电子研究所,陕西西安710071

出　　处：《西安电子科技大学学报》2004年第1期32-35,共4页Journal of Xidian University

基　　金：国家部委预研基金资助项目(41308010205);教育部跨世纪优秀人才培养基金资助项目

摘　　要：为了有效地解决困扰现场可编程门阵列发展的功耗延时积问题,采用集成电路互连的分段式结构和低压摆电路,提出了一种基于互连的最优功耗延时积现场可编程门阵列设计方法.对于产生传输线效应的现场可编程门阵列互连,通过优化互连的段数,在互连最外面的输入端和输出端分别连接低压摆电路的驱动部分和接收部分,在内部的每段互连之间插入最优尺寸的缓冲部分.理论与模拟表明,用这种方法设计的现场可编程门阵列能使功耗延时积减小近一个数量级,同时较好地保持现场可编程门阵列的面积性能.With the segmentation structure and low-swing circuit of the integrated circuit interconnect, an optimal design method is developed for solving the challenge of the FPGA energy delay product. Optimizing the segmentation number of the FPGA interconnect with transmission line effects, the driving unit and receiving unit of the low-swing circuit are respectively connected to the input and output of the interconnect, and optimal size repeaters are inserted in the segmented interconnect. Both theoretical and experimental results show that the improvement of the FPGA energy delay product with this new technique is about an order of magnitude when compared to existing commercial architectures while keeping the good area performance of FPGA.

关 键 词：现场可编程门阵列互连 RLC模型 分段式结构 低压摆电路 功耗延时积 深亚微米集成电路 

分 类 号：TN43[电子电信—微电子学与固体电子学]