DWT和位平面编码器的接口存储控制设计  

The interface memory control design between DWT and bit-plane encoder

作　　者：梅魁志[1] 郑南宁[1] 王勇[1] 兰旭光[1] 吴勇[1] 

机构地区：[1]西安交通大学人机所,西安710049

出　　处：《微电子学与计算机》2004年第1期98-101,共4页Microelectronics & Computer

基　　金：国家863超大规模集成电路设计专项(2002AA1Z1440)

摘　　要：在JPEG2000专用集成电路设计中,DWT和Tier1编码之间的接口存储器设计直接影响DWT变换的系数存储和LL子带数据的再读取,及为给Tier1的位平面编码器提供码块数据。本文使用了二块片内DPRAM实现上述存储,提出了一种简单而高效的读写策略,并实现了该方法的FPGA仿真,性能分析表明DWT和位平面编码器并行性接近90%。The memory control design between DWT module and Tier1module in JPEG2000chip design is very impor tant,for it is a necessary part of DWT and also splits the sub-band coefficients into code blocks to generate the input da ta of the bit-plane encoder.Two on-chip DPRAM architecture is used for the design and an efficient strategy to imple ment the memory access is proposed.The design has been finished the gate-level time simulation in Altera Quartus2.1and the parallel processing between the DWT module and the Tier1module has gained the performance of90%.

关 键 词：DWT变换 位平面编码器 集成电路 电路设计 接口存储器 图像编码 

分 类 号：TN919.81[电子电信—通信与信息系统]