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作 者:陈洪存[1] 王矜奉[1] 王文新[1] 苏文斌[1] 臧国忠[1] 亓鹏[1] 王春明[1]
机构地区:[1]山东大学物理与微电子学院晶体材料国家重点实验室,济南250100
出 处:《压电与声光》2004年第1期42-44,共3页Piezoelectrics & Acoustooptics
基 金:国家自然科学基金资助项目(50072013)
摘 要:研究了Cd对(Co,Nb)掺杂SnO2压敏材料电学性质的影响。组分为97.65%SnO2+0.75%Co2O3+0.10%Nb2O5+1.50%CdO的压敏电阻具有最大非线性系数(α=22.2)和最高的势垒(φB=0.761eV)。当CdO的摩尔分数从0增加到3%时,(Co,Nb)掺杂SnO2压敏电阻的击穿电压从366V/mm增大到556V/mm,1kHz时的相对介电常数从1429减小到1108。晶界势垒高度测量揭示,SnO2的晶粒尺寸的减小是击穿电压增高和介电常数减小的主要原因。对Cd掺杂量增加引起SnO2晶粒减小的根源进行了解释。The effect of CdO on the electrical properties of the (Co, Nb)-doped SnO_2 varistors was investigated. An addition of 1.50 %CdO makes the varistor with composition of 97.65%SnO_2+0.75%Co_2O_3+0.10%Nb_2O_5+1.50% CdO in the highest nonlinear coefficient (α=22.2) and the highest potential barrier height(φ_B=0.761eV). It was found that the breakdown voltage of the SnO_2 based varistors increased from 366 V/mm to 556V/mm, and the relative dielectric constant at 1 kHz of the SnO_2 based varistors decreased from 1 429 to 1 108 with increasing CdO concentration from 0 to 3 %. Measurement of the barrier height at grain boundaries reveals that the decrease of the SnO_2 grain size with increasing CdO concentration from 0 to 3 % is the reason for raising the breakdown voltage and lowering the dielectric constant. The origin for the deduction of SnO_2 grain size with increasing CdO concentration was also explained.
分 类 号:TN379[电子电信—物理电子学]
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