I/O通讯中时序和同步的高级综合  

High-Level Synthesis of Timing and Synchronization in I/O Communication

作　　者：孟晗[1] 刁岚松[1] 刘明业[1] 

机构地区：[1]北京理工大学信息科学技术学院计算机科学工程系,北京100081

出　　处：《北京理工大学学报》2004年第2期125-128,149,共5页Transactions of Beijing Institute of Technology

基　　金：国家部委预研项目(200208010408).

摘　　要：研究VHDL中表示时序和约束的方法和综合前后模拟一致性在不同设计中的含义.根据这一含义,说明并实现了VHDL中循环语句的综合方法、条件语句和分支语句的综合方法,并实现了与循环有关的其它语句的综合.通过典型的例子给出程序的运行结果,说明实现的方法具有正确性和实用性.Studies the ways with which VHDL expresses its timing and synchronization and the meanings of consistency between pre- and post- synthesis simulation of VHDL source description. For different meanings the method of synthesizing different statements is explained and realized. The ways of synthesis 'loop statement', 'if statement' and 'case statement' are different under different VHDL timing and constraints. Synthesis of other statements related to the loop is also realized. The correctness and practicability of the method given is shown after running some typical examples.

关 键 词：高级综合 VHDL 循环语句 

分 类 号：TP229[自动化与计算机技术—检测技术与自动化装置]