基于重构技术的并行乘法累加器结构  

Architecture of Parallel Multiply-Accumulate Unit(MAC) Based On Reconfiguration Technology

作　　者：李莺[1] 陈杰[1] 

机构地区：[1]中国科学院微电子中心,北京100029

出　　处：《微电子学与计算机》2004年第3期109-112,共4页Microelectronics & Computer

摘　　要：实时信号处理系统要求数字信号处理器具有更高的速度和更低的功耗。文章提出的新型乘法累加器,具有在不同模式下分别处理16位与32位数据,或16位与32位数据混合运算能力。本运算结构采用由三个16位乘法器重构一个32位运算单元,可调用其中一至三个乘法累加模块处理不同精度的数据达到了高速度、低功耗的设计要求。在32位工作模式下数据处理速度可以达到16位乘累加器的水平。Real-time signal processing system requires the digital signal processor (DSP) has lower power and higher speed. The multiply-accumulate unit (MAC) specified in this paper describes a novel architecture. It can handle operation of 16-bit and 32-bit separately or mixed operation of them in different modes. This 32-bit MAC unit is reconfigured by three 16-bit multipliers, from one to tree low-bit MAC units could be chosen to complete data of certain precisions to reach the goal of high speed and low power. In the 32-bit operation mode, the above-mentioned novel architecture of 16-Bit/32-Bit parallel multiply-accumulate unit (MAC) based on reconfiguration technology has the speed as high as that of 16-bit fast MAC unit.

关 键 词：并行乘法累加器 重构技术 数字信号处理器 数据处理 分割算法 

分 类 号：TP332.22[自动化与计算机技术—计算机系统结构]