用Verilog硬件描述语言设计数字计时器  

Designing Digital-Calculagraph By Verilog HDL

作　　者：欧阳玲[1] 宋克[2] 王双红[1] 

机构地区：[1]中原工学院电气工程系,河南郑州450007 [2]西安交通大学电信学院,陕西西安710049

出　　处：《中原工学院学报》2004年第2期73-75,共3页Journal of Zhongyuan University of Technology

摘　　要：介绍了一种利用Verilog硬件描述语言设计数字计时器的方案 ,具有成本低、设计简单、容易扩展的特点 .The paper introduces a design project of Digital\|Calculagraph by Verilog HDL. Using the Hardware Description language to design Digital\|Calculagraph has advantages such as low cost, simply to design, easy to expand. It analyzes the total configuration of the system, gives the HDL description of each part of logic electric circuits and the synthetical result of the electric circuit.

关 键 词：VERILOG 硬件描述语言 数字计时器 设计 逻辑电路 HDL 电路综合 

分 类 号：TN79[电子电信—电路与系统]