大数快速模幂算法的硬件设计  

Hardware Design of Fast Module Exponential Algorithm

作　　者：范明钰[1] 王建华[2] 王光卫[1] 

机构地区：[1]电子科技大学计算机学院,四川成都610054 [2]北京航空航天大学计算机学院,北京100083

出　　处：《西南交通大学学报》2004年第3期306-310,共5页Journal of Southwest Jiaotong University

基　　金：国家自然科学基金资助项目(60272091)

摘　　要：将快速模幂算法、快速模乘算法和快速加法组合,提出了一种大数快速RSA算法,并利用该算法给出了一个RSA公开密钥的加解密硬件实现方案.首先采用m ary方法,减少模乘运算次数;其次采用Montgomery改进算法,减少模加运算次数;最后,采用高速加法器并调整加法与乘法的结构使其同时运行,以节约资源.对于1024位操作数,在100MHz时钟频率下,加密速率约为390kbit/s.Fast module exponential algorithm, fast module multiplication algorithm and fast module addition algorithm were integrated to form a hybrid fast RSA algorithm for large number operations. A hardware scheme for implementation of RSA key was proposed using the proposed algorithm. In the algorithm, m-ary method is used in the first stage to reduce multiplication times, then modified Montgomery method is used to decrease addition times, and finally fast adders and multiplication unit are made to work synchronously by adjusting their structures. A processing speed of 390 kbit/s at (100 MHz) clock was achieved for a 1 024 bit key operand.

关 键 词：算法 模幂 模乘 RSA Montgomery方法 选择清除累加器 

分 类 号：TN492[电子电信—微电子学与固体电子学] TP309[自动化与计算机技术—计算机系统结构]