应用于FPGA芯片的边界扫描电路  

A Boundary-Scan Test Circuit for FPGA's

作　　者：马晓骏[1] 童家榕[1] 

机构地区：[1]复旦大学微电子系专用集成电路国家重点实验室,上海200433

出　　处：《微电子学》2004年第3期326-329,333,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60076014);教育部高等学校博士学科点专项科研基金资助项目(2000024623)

摘　　要：　针对在FPGA芯片中的应用特点,设计了一种边界扫描电路,应用于自行设计的FPGA新结构之中。该电路侧重于电路板级测试功能的实现,兼顾芯片功能的测试;同时,加入了器件编程功能。在电路设计中采用单触发器链寄存器技术,节省芯片面积。版图设计采用0.6μm标准CMOS工艺,并实际嵌入FPGA芯片中进行流片。该电路可实现测试、编程功能,并符合IEEE1149.1边界扫描标准的规定,测试结果达到设计要求。A boundary scan circuit is designed based on the characteristics of FPGA's. The circuit is used in a self-designed new architecture of FPGA. The design emphasizes the function of PCB-level test while paying attention to the chip-level test. And device-programming function is also added into the circuit. In the design, shared register chain is adopted to save chip area. The layout, which is designed with 0.6 μm standard CMOS process, is integrated into our new FPGA chip for processing. Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.

关 键 词：边界扫描 现场可编程门阵列 可测试性设计 器件编程 

分 类 号：TN407[电子电信—微电子学与固体电子学]