28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I  

作　　者：Ali Mohsen Adnan Harb Nathalie Deltimple Abraham Serhane 

机构地区：[1]Department of Electrical and Electronics Engineering, Lebanese International University, Beirut, Lebanon [2]IMS Laboratory, University of Bordeaux, Talence cedex, France [3]Department of Industrial Engineering, Lebanese International University, Beirut, Lebanon

出　　处：《Circuits and Systems》2017年第4期93-110,共18页电路与系统（英文）

摘　　要：Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.

关 键 词：UTBB FD-SOI: Ultra-Thin Body and Box Fully Depleted Silicon on Insulator Tri-Gate FINFET DIBL: Drain Induced Barrier Lowering 

分 类 号：TN3[电子电信—物理电子学]