28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II  

作　　者：Ali Mohsen Adnan Harb Nathalie Deltimple Abraham Serhane 

机构地区：[1]Department of Electrical and Electronics Engineering, Lebanese International University, Beirut, Lebanon [2]IMS Laboratory, University of Bordeaux, Talence Cedex, France [3]Department of Industrial Engineering, Lebanese International University, Beirut, Lebanon

出　　处：《Circuits and Systems》2017年第5期111-121,共11页电路与系统（英文）

摘　　要：This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.

关 键 词：UTBB FD-SOI: Ultra-Thin Body and Box Fully Depleted Silicon on Insulator Tri-Gate FINFET DIBL: Drain Induced Barrier Lowering 

分 类 号：TN3[电子电信—物理电子学]