Timed Petri Net Models of Shared-Memory Bus-Based Multiprocessors  

作　　者：Wlodek M. Zuberek 

机构地区：[1]Department of Computer Science, Memorial University, St. John’s, Canada

出　　处：《Journal of Computer and Communications》2018年第10期1-14,共14页电脑和通信（英文）

摘　　要：In shared-memory bus-based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory). This contention reduces the performance of processors and imposes a limitation of the number of processors that can be used efficiently in bus-based systems. Since the multi-processor’s performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared-memory bus-based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system. The results illustrate very well the restriction on the number of processors imposed by the shared bus. All performance characteristics presented in this paper are obtained by discrete-event simulation of Petri net models.In shared-memory bus-based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory). This contention reduces the performance of processors and imposes a limitation of the number of processors that can be used efficiently in bus-based systems. Since the multi-processor’s performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared-memory bus-based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system. The results illustrate very well the restriction on the number of processors imposed by the shared bus. All performance characteristics presented in this paper are obtained by discrete-event simulation of Petri net models.

关 键 词：SHARED-MEMORY MULTIPROCESSORS BUS-BASED MULTIPROCESSORS TIMED PETRI NETS Discrete-Event Simulation 

分 类 号：R73[医药卫生—肿瘤]