32位快速乘法器的设计  

Design of 32-bit multiplier with good speed performance

作　　者：詹文法[1] 汪国林[1] 杨羽[1] 张珍[1] 

机构地区：[1]合肥工业大学电气与自动化工程学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2004年第9期1099-1102,共4页Journal of Hefei University of Technology：Natural Science

摘　　要：高性能乘法器是现代微处理器中的重要部件,乘法器完成一次乘法操作的周期基本上决定了微处理器的主频。传统的乘法器的设计,在最终的乘积项求和时,常采用阵列相加或叠代相加的方法,不适用中小规模的微处理器的设计。该文提出的32位乘法器,采用了Booth编码、4-2压缩器、Wallace树算法以及超前进位加法器等多种算法和技术,在节约面积的同时,获得了高速度的性能。A multiplier with good speed performance is a very important unit in the modern microprocessors because the cycle that a multiplier completes one multiplication operation determines the main frequency of the microprocessor. In summing of the last product in the traditional multiplier design, the array or iteration summing method is used, which is not suitable to the design of small or middle scale integration circuit. A 32-bit multiplier is presented in which many methods, such as Booth algorithm, 4-2 compressors, Wallace tree algorithm,and carry-lookahead adder, are applied, which results in high speed performance.

关 键 词：乘法器 BOOTH编码 超前进位加法器 Wallace树算法 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]