VHDL硬件描述语言教学探讨  

Teaching Experience in VHDL Hardware Description Language

作　　者：龚兰芳[1] 

机构地区：[1]广东水利电力职业技术学院,广东广州510635

出　　处：《广东水利电力职业技术学院学报》2009年第4期29-32,共4页Journal of Guangdong Polytechnic of Water Resources and Electric Engineering

摘　　要：在VHDL语言课程教学中,信号与变量的使用和VHDL设计中电路的简化问题是学生在学习过程中最难掌握的两个问题,对此通过实例进行详细阐述,并从描述方法、逻辑函数、算术功能等方面分析VHDL设计中容易引起电路复杂化的原因,讨论几种提高器件利用率的VHDL优化设计方法。There are two difficult points in teaching and learning VHDL,which are signal and variable application and predigesting of VHDL circuit design.With detailed example,this paper analyzes the reasons why circuit complication is caused in VHDL design from the aspects of description means,specific logic function and arithmetic.Then,several optimized VHDL design methods are also discussed to improve element profitability.

关 键 词：VHDL 信号 变量 优化设计 

分 类 号：TN402[电子电信—微电子学与固体电子学]