一种大频偏抗边带错锁的数字锁相环设计  

Design of DPLL for Anti-False-Lock with Large Frequency Offset

作　　者：刘亚欢[1] 田宇[1] 李国通[1] 

机构地区：[1]中国科学院微小卫星联合重点实验室,上海200050

出　　处：《遥测遥控》2010年第1期1-4,共4页Journal of Telemetry,Tracking and Command

摘　　要：在小卫星遥测系统中,地面站接收信号伴随着大多普勒频偏,副载波会落入主载波的多普勒频偏的范围之内,数字锁相环对主载波的跟踪必须避免边带错锁。提出一种新的数字锁相环结构,通过频谱分析辅助,初始频差和环路带宽被减小,副载波不会落入环路带宽之内;在环路中采用cic低通滤波下抽样滤除副载波分量,副载波对锁相环的影响得以消除。仿真结果表明,该锁相环在大频偏情况下能够很好地消除边带错锁。在实际的地面站遥测接收机中,该锁相环也能够很好地工作。The signal received from the ground station in the micro-satellite telemetry system is usually with large Doppler frequency offset,and the vice carrier signal will lap over the Doppler frequency offset of the main carrier signal.DPLL(Digital Phase-Locked Loop) tracking the main carrier signal must avoid the false-lock on the vice carrier signal.This paper designs a DPLL with new structure.The frequency offset and the loop bandwidth are degraded with the aid of spectrum analysis.Then the vice carrier will not lap over the loop bandwidth.A cic lowpass filter is adopted to eliminate the vice carrier signal and the vice carrier will not influence the DPLL.Simulation shows that this DPLL eliminates the false-lock in large frequency offset environment.In the real telemetry receiver of the ground station,this DPLL works very well.

关 键 词：遥测 多普勒频偏 边带错锁 数字锁相环 

分 类 号：TN911.8[电子电信—通信与信息系统]