基于Verilog的CAN总线协议验证模型库的建立  

Establishment of CAN Bus Protocol Verification Model Using Verilog

作　　者：吕易俗 田文杰[1] 李翔宇[2] 殷树娟[1] 包舒 孙少东[2] 

机构地区：[1]北京信息科技大学理学院,北京100192 [2]清华大学微电子所,北京100038

出　　处：《微电子学与计算机》2015年第3期122-126,131,共6页Microelectronics & Computer

基　　金：国家自然科学基金项目(61376057);北京市自然科学基金项目(4122030);北京市自然科学重点基金项目(B)(KZ201511232037)

摘　　要：随着集成电路芯片设计难度的提高,对芯片设计的验证也变得越来越复杂.能够高效全面的验证,同时缩短整个开发周期,降低设计成本是验证工作者面对的重要问题.对此基于Verilog HDL设计了CAN总线节点的RTL验证模型,并依据建立验证模型的需求,增加了错误注入功能及用户接口,从而简化测试平台开发的复杂度,最终完成对被测目标中CAN模块的协议完整性的测试.通过对典型操作实例的分析,验证了该方法的有效性.With increasing difficulty of the integrated circuit chip design,verification has become increasingly complex,fully capable of comprehensive verification,shorten the development cycle,reduce design cost are becoming particularly important issues for validators.This article is based on Verilog HDL to design a CAN bus verification model to validate CAN bus nodes.In order to meet the needs of the verification,capabilities of error injection and user interface are added,these functions simplify the complexity of the test platform.Finally,the integrity test of the DUT's CAN protocol within bus model is achieved.Our analysis of typical examples verify the effectiveness of the method.

关 键 词：验证 验证模型 CAN总线 VERILOG 

分 类 号：TN402[电子电信—微电子学与固体电子学]