16位超前进位加法器的设计  

Design of 16-bit carry look-ahead adder

作　　者：谢莹[1] 陈琳[1] 

机构地区：[1]安庆师范学院教育技术系,安徽安庆246011

出　　处：《合肥工业大学学报（自然科学版）》2004年第4期450-454,共5页Journal of Hefei University of Technology：Natural Science

摘　　要：电子计算机是由具有各种逻辑功能的逻辑部件组成的,加法器就属于其中的组合逻辑电路。如果对传统的加法器电路进行改进,在超前进位链的基础上,用一种新的超前进位链树的设计方法不仅可以克服串行进位加法器速度低的缺点,也可以解决单纯的超前进位加法器带负载能力不足等问题,从而在实际电路中使加法器的运算速度达到最优。根据这种理论,可以推导得到最优的任意位加法器。A computer is comprised of some logic parts which have serial logic functions,and the adder is one of the combine logic circuits. In order to improve the traditional adder circuit,based on the carry look-ahead technology, a new design of carry look-ahead chain is presented so that the low speed of serial adders and the less carry capacity of the pure carry look-ahead adder can be overcome. Thus the optimum compute speed can be achieved in the real circuit. Based on the presented idea, the excellent random bit adder can be deduced.

关 键 词：半加器 全加器 超前进位加法器 4位超前进位加法器 16位超前进位加法器 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]