嵌入式可重构DSP处理器的指令译码器设计  

Design of Instruction Decoder of Reconfigurable Embedded DSP Processor

作　　者：韩亮[1] 陈杰[1] 陈晓东[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2004年第7期91-94,146,共5页Microelectronics & Computer

摘　　要：在对我们研发的代号为CoStar的嵌入式可重构32位DSP(DigitalSignalProcessing)处理器的结构作简要介绍的基础上,着重阐述了其指令译码器的设计。文章的重点放在我们提出的一些新颖的设计思想上:为支持CoStar的复杂流水线、SIMD(SingleInstructionstreamoverMultipleDatastreams)和可重构而采用的相对集中的分布式译码、多模式指令复用等技术;为降低译码器的面积和功耗而采用的嵌套式的分类译码、类型合并、译码预判、信号合并等技术。Based on a brief introducing of CoStar, which is a reconfigurable embedded 32-bit Digital Signal Processor designed by us, we will discuss in detail the design of its Instruction Decoder. The paper will focus on the novel techniques employed in the design. On the one hand, in order to cooperate with the complex pipeline, SIMD (Single Instruction stream over Multiple Data streams), and reconfigurable structure of CoStar, we present the techniques of Distributed Decoding which has a relatively concentrative characteristic, and Instruction Sharing under Multiple-Mode. On the other hand, in order to reduce the chip area and power consumption, we present Nesting Type-Separated Instruction Decoding, Type Merging, Instruction Pre-decoding, and some other techniques. These techniques are also suitable to design other processors.

关 键 词：DSP处理器 指令 译码器 分布式译码 分类译码 

分 类 号：TN911[电子电信—通信与信息系统]