集成电路时间延迟优化分析与模拟  

Optimal Analysis and Simulation of Time Delay in Integrated Circuits

作　　者：李文石[1] 唐璞山[2] 许杞安 章焱[1] 

机构地区：[1]苏州大学电子信息学院微电子学系,江苏苏州215021 [2]复旦大学微电子学系,上海200433 [3]世宏科技 (苏州 )公司器件实验室

出　　处：《微电子学》2004年第6期655-657,662,共4页Microelectronics

摘　　要：　基于Elmore模型,优化分析了N级二维CMOS传输门链和N门三维双栅SOIIC的时间延迟,给出了HSPICE模拟结果。研究表明,由相同尺寸管子构成的N级二维CMOS门链,当把N级分作每3级为一组并且以缓冲门相间隔时,总时延存在极小值;由宽度尺寸比为3的三级不等尺寸管子所构造的传输门链间隔以缓冲门,也存在最小时延;当N门三维双栅SOIIC分为6个器件层时,可获得最小的时间延迟。Time delay of N-stage CMOS transmission gate chain and N-gate 3D double-gate SOI IC is optimally analyzed based on Elmore model, and HSPICE simulation results are presented. The study has come to the following conclusions: 1) with each buffer inserted into every other three stages in the N-stage CMOS transmission gate chain, there is minimum delay time; 2) under the same condition as 1 and with N/PMOS device width ratio =3 in every 3-stage, there is also minimum delay time; 3) with m = 6 device-layers for for N-gate 3D DG SOI IC, there is minimum delay time.

关 键 词：Elmore模型 CMOS 传输门链 三维IC 时间延迟 HSPICE模拟 

分 类 号：TN47[电子电信—微电子学与固体电子学]