一种采用新的相频检测技术的CMOS数字锁相环  

A CMOS Digital PLL with a New Phase-frequency Detection Technique

作　　者：刘素娟[1] 周安宇[1] 陈建新[1] 蔡黎明[2] 徐东升[2] 

机构地区：[1]北京工业大学光电子实验室,北京100022 [2]中国华大集成电路设计中心,北京100015

出　　处：《固体电子学研究与进展》2004年第4期476-481,共6页Research & Progress of SSE

基　　金：国家高科技研究发展计划资助项目 (NO .2 0 0 2AA1Z12 90 )

摘　　要：提出了一种新型的数字锁相环 (DPLL) ,它的相频检测器采用全新的设计方法 ,与传统电荷泵锁相环相比 ,具有快速锁定、低抖动、低功耗、频率范围宽、且能消除相位“死区”的优点。锁相环在 1.8V外加电源电压时 ,工作在 6 0～ 6 0 0MHz宽的频率范围内 ,最大功耗为 3.5mW。采用分数分频技术 ,具有较小的输出频率间隔 ,并利用Σ Δ调制改善相位噪声性能。设计采用 0 .18μm ,5层金属布线工艺。峰 峰相位抖动小于输出信号周期(Tout)的 0 .5 % ,锁相环的锁定时间小于参考频率预分频后信号周期 (Tpre)的 15 0倍。A low-power digital phase-locked loop(DPLL) based on a new digital phase-frequency detection technique is presented. Compared with the traditional charge-pump PLL, the proposed DPLL eliminates phase “dead zone” and has the advantages of fast-locking, low-jitter, low-power, and a wide locking range. The DPLL works from 60 MHz to 600 MHz with a maximum power consumption of 3.5 mW at a supply voltage of 1.8 V. It also features a fractional-N synthesizer with digital 2 nd -order sigma-delta noise shaping, which can achieve the small step size and improve phase-noise spectrum. The DPLL has been implemented in a 0.18 μm quintuple-metal CMOS process. The peak-to-peak jitter is less than 0.5% of the output period( T out ), and the lock time is less than 150 times of the reference clock period after the predivider( T pre )

关 键 词：数字锁相环 相频检测 压控振荡器 分数分频 互补金属氧化物半导体 

分 类 号：TN431[电子电信—微电子学与固体电子学]