一种采用半速结构的CMOS串行数据收发器的设计  

CMOS Serial Transceiver with Half-Rate Architecture

作　　者：黄林[1] 郭淦[1] 叶菁华[1] 陈一辉[1] 洪志良[1] 

机构地区：[1]复旦大学微电子学系,上海200433

出　　处：《Journal of Semiconductors》2005年第1期180-186,共7页半导体学报（英文版）

摘　　要：设计了一种单片集成的CMOS串行数据收发器 .该收发器用于线上速率为 1 2 5Gb/s的千兆以太网中 ,全集成了发送和接收的功能 ,主要由时钟发生器、时钟数据恢复电路、并串 /串并转换电路、线驱动器和均衡器组成 .为了降低系统设计难度和电路功耗 ,收发器采用了半速率时钟结构 .电路采用 1 8V 0 18μm 1P6MCMOS数字工艺 ,芯片面积为 2 0mm× 1 9mm .经CadenceSpectre仿真验证以及流片测试 ,电路工作正常 。The design of a monolithic integrated CMOS serial transceiver used in 1.25Gb/s Gigabit Ethernet is described.The transceiver comprises full transmit and receive functions,mainly including clock generator,clock and data recovery circuit,serializer/deserializer,line driver and equalizer.The half-rate architecture is adopted to reduce the complexity of design and save power.The chip is designed in 1.8V 0.18μm 1P6M CMOS digital process and its active area is 2.0mm×1.9mm.Simulated by Cadence Spectre and tested with chipset,the circuit works properly.

关 键 词：收发器 时钟发生器 时钟数据恢复 线驱动器 均衡器 并串/串并转换 

分 类 号：TN432[电子电信—微电子学与固体电子学]