单电子晶体管全加器电路设计  

A Full Adder Realization for Single-Electron Transistors

作　　者：马彦芬[1] 

机构地区：[1]河北工程技术高等专科学校,河北沧州061001

出　　处：《微纳电子技术》2005年第3期111-114,共4页Micronanoelectronic Technology

摘　　要：基于单电子晶体管(SET)的I-V特性和二叉判别图数字电路的设计思想,改进了二叉判别图(BDD))单元,得到了一类基本逻辑门电路,进而提出了一种由11个BDD)单元即22个SET构成的全加器电路单元。SPICE宏模型仿真结果验证了设计的正确性。Based on the I-V characteristics of single-electron transistors (SETs) and the concepts of binary decision diagram (BDD), BDD unit is improved and some basic logic circuits are constructed. Therefore, a full adder, which is composed of 11 BBD units, namely 22 SETs, is proposed. The accuracy is validated by SPICE macro-model of SET.

关 键 词：单电子晶体管 二叉判别图 全加器 SPICE宏模型 

分 类 号：TN713[电子电信—电路与系统]