台面刻蚀对电力SITH器件特性的影响  

The impact of mesa etching on the device characteristics of power SITH

作　　者：拥冬青 李思渊[1] 王永顺[1] 

机构地区：[1]兰州大学物理科学与技水学院,甘肃兰州730000

出　　处：《兰州大学学报（自然科学版）》2005年第2期92-94,共3页Journal of Lanzhou University(Natural Sciences)

摘　　要：分析了台面刻蚀程度对埋栅型STTHⅠ-Ⅴ特性的影响,表明台面刻蚀不足或过蚀程度太深都可能造成栅电极电压不能有效施加到栅体上,从而限制了栅体的控制能力,影响器件性能,严重时会导致特性异常,这是影响器件成品率的一个重要因素.台面刻蚀必须刻透外延层并适当过腐蚀,过腐蚀程度宜控制在栅体结深的1/10左右.The impact of the mesa etching degree on the Ⅰ-Ⅱ characteristics of the buried gate structure SITH are discussed, with the conclusion that both deficient etching and far over-etching could divorce the gate electrode from the gates. This weakens the control ability of the gates and influences the devices' performance. Sometimes it may transfer the devices'Ⅰ-Ⅱ characteristics. Finally, it is pointed out that mesa etching must eat off the epitaxial layer above the gate walls and that epilayer over-etching is necessary. It is suitable that the over-etching degree should be controlled within ten percent of the gate junction depth.

关 键 词：静电感应晶闸管 台面刻蚀 I-V特性 

分 类 号：TN323[电子电信—物理电子学]