基于SoC平台设计的H.264/AVC CAVLC解码器  

Design of H.264/AVC CAVLC Decoder Based on SoC Platform

作　　者：路奇[1] 方向忠[1] 刘凌志[1] 

机构地区：[1]上海交通大学图像通信与处理研究所,上海200030

出　　处：《电视技术》2005年第4期29-32,共4页Video Engineering

基　　金：国家"863"高技术研究发展计划资助项目:"高清晰度电视SoC平台"(2003AA1Z1070)

摘　　要：提出了一种基于SoC平台的CAVLC解码器。在尽量减少时钟消耗的前提下,此解码器可以解码每个变换块中变换系数的熵编码码流,并将结果按照块扫描顺序并行输出。通过在XILINX的ISE6.0FPGA开发软件下仿真及分析表明,在120MHz时钟时可以满足10Mb/s码率下H.264标准中Level3.0的性能要求。Based on SoC Platform, this paper presents a VLSI architecture for CAVLC decoder. While minimizing the use of clock cycles, it could decode the coded stream of transform coefficients in each block and output the decoded coefficients in zigzag scanning order. And this decoder can be used as a coprocessor on SoC platform. Simulation in ISE6.0 FPGA development software shows that its maximal working frequency is around 120 MHz and could fulfill the performance requirement of Level 3.0 in H.264 standard.

关 键 词：H.264/AVC 变长编码 解码器 

分 类 号：TN919.81[电子电信—通信与信息系统]