IP芯核测试响应的零混叠空间压缩  

Zero-aliasing Space Compaction of Test Response for IP Cores

作　　者：谢永乐[1] 孙秀斌[1] 王玉文[1] 胡兵[1] 陈光 

机构地区：[1]电子科技大学自动化工程学院,成都610054

出　　处：《仪器仪表学报》2005年第4期395-398,421,共5页Chinese Journal of Scientific Instrument

基　　金：国家自然科学基金 (90 4 0 70 0 7);教育部科学技术研究重点项目基金资助。

摘　　要：提出了一种片上系统内嵌IP芯核测试响应的空间压缩方法。将内建自测试中的测试矢量(样式)计算器状态作为空间压缩器的输入,只需利用被测芯核的测试集及对应无故障响应便能实现零混叠空间压缩,具有经单步压缩便可实现最大压缩比的特点,故在测试时间开销上优于经两步(模式)压缩才能实现零混叠的方法[1～2 ]。该方法不要求测试矢量的排序[3] ,故对IP芯核的确定性测试及伪随机测试皆适用。A novel space compaction approach for test response of embedded Intellectual Property cores on system-on-a-chip is proposed. The states of test vector/pattern counter are connected to the inputs of the compactor, thus zero-aliasing space compaction can be achieved only making use of the precomputed test set of core under test and its fault-free response. Advantages of this approach include maximum compaction ratio and implementation only by single step compaction, so with respect to the test time consumption, it excels those in which zero-aliasing is obtained via two step[1] or two mode[2] compaction. Sorting of test vectors is not demanded[3], so it is useful both for deterministic test and pseudo-random test of IP cores. ©, 2005, Science Press. All right reserved.

关 键 词：IP芯核 空间 混叠 响应 测试矢量 内建自测试 伪随机测试 确定性测试 压缩方法 片上系统 测试时间 压缩器 计算器 测试集 压缩比 

分 类 号：TN702[电子电信—电路与系统] TU238.2[建筑科学—建筑设计及理论]