可综合的基于Verilog语言的有限状态机的设计  

Design for Synthesizable Finite State Machine Based on Verilog Language

作　　者：刘德贵[1] 李便莉[2] 

机构地区：[1]西安电子科技大学综合业务网国家重点实验室,陕西西安710071 [2]西安电子科技大学通信工程学院,陕西西安710071

出　　处：《现代电子技术》2005年第10期116-118,共3页Modern Electronics Technique

摘　　要：Verilog HDL是一种硬件描述语言,他不仅可以在门级和寄存器传输级描述硬件,也可以在算法级对硬件加以描述,因此将采用Verilog HDL语言描述的设计转变成逻辑门构成的电路绝非简单的处理过程。状态机是数字系统的控制单元,包括时序逻辑和组合逻辑,语言描述较为抽象,如果句柄编写不规范,综合工具就很难把抽象思维变为门级电路。由于Verilog HDL 语言本身的特点,许多面向仿真的语句虽然符合语法规则却不能综合,这在设计中必须避免。本文介绍了Verilog HDL语言的综合实质,研究了编写可综合的状态机的方法、步骤以及综合原则,具有一定的参考价值。VerilogHDL is a hardware description language, which can describe hardware not only in gate level and registertransfer level but also in algorithmic level. Therefore, changing designs in VerilogHDL into circuits made of logic gates is not a simple process. FSM is the control unit of a digital system, including timing logic and combination logic, and the language description is very abstract, if the handle is not compiled in standard, it is very difficult to change the abstract thought into a gate level circuit by Synthesis tool.Due to the inherent characteristics of VerilogHDL, many statements and structures based on simulation and according with syntax rules could not be transformed into logic unit. So we should avoid to use these statements and structure. This article introduces the essence of VerilogHDL synthesis, studies the way, steps of how to write synthesizable FSM.It studies synthesis principles as well. All these have certain value for reference.

关 键 词：VERILOGHDL语言 FSM状态机 综合 逻辑 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]