注入同步锁相环式时钟恢复电路MMIC的设计和实现  

Design and Realization of Clock Recovery MMIC Based on Injection-synchronized Phase-locked Loop

作　　者：仇应华[1] 王志功[1] 朱恩[1] 冯军[1] 熊明珍[1] 夏春晓[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《固体电子学研究与进展》2005年第2期184-189,共6页Research & Progress of SSE

基　　金：国家863计划项目2001AA312060资助课题

摘　　要：设计了单片集成的超高速NRZ码时钟恢复电路,该电路采用注入同步压控振荡器结合锁相环的结构,在保持普通PLL型时钟恢复电路优点的同时,加快了锁相环的响应速度,提高了系统的稳定度。利用法国OMMIC公司的0.2μmGaAsPHEMT,制造了MMIC芯片,在输入速率为8.2Gb/s、长度为223-1伪随机序列的情况下,输出时钟的均方根抖动为1.6ps。芯片面积为1.5mm×2mm。采用-5V电源供电,功耗约为600mW。A PLL (phase-locked loop)-type clock recovery MMIC with injection-synchronized voltage-controlled oscillator is realized by using OMMIC's 0.2 μm GaAs PHEMT technology. The measured rms jitter of recovered clock signal is 1.6 ps under the stimulation of a 2~23 -1-bit-long pseudorandom bit sequence at the bit rate of 8.2 Gb/s. The chip area is 1.5 mm×2 mm. The DC power consumption is 600 mW under a -5 V supply.

关 键 词：时钟恢复 锁相环 注入同步压控振荡器 

分 类 号：TN43[电子电信—微电子学与固体电子学]