基于Verilog HDL语言的32X8 FIFO设计  

The Design of 32X8 FIFO Based on Verilog HDL

作　　者：夏传红[1] 王祖强[1] 李秀娟[1] 

机构地区：[1]山东大学信息科学与工程学院,山东,济南,250100

出　　处：《信息技术与信息化》2005年第2期54-56,共3页Information Technology and Informatization

摘　　要：介绍了FIFO的基本概念、设计方法和步骤,采用了一种新颖的读、写地址寄存器和双体存储器的交替读、写机制,实现了FIFO的基本功能,同时使本3 2X8FIFO拥有可同时读、写的能力,完全基于VerilogHDL语言实现了电路功能并应用Synopsys公司的DesignCompiler和VCS对其进行综合、仿真。This thesis introduces the FIFO's basic concept, design method and steps, and a novel mechanism of reading and writing FIFO with two separate memories. The reading and writing operation will alternate between the two memories, thus this FIFO can be read and written in the same time. The design is based on the Verilog HDL language, sythesized with Design Compiler and simulated with VCS of the Synopsys company.

关 键 词：Verilog HDL语言 FIFO Synopsys公司 Design 地址寄存器 设计方法 基本功能 电路功能 存储器 VCS 仿真 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]