一种新型高速高分辨率采样保持电路  

A New High-Speed and High-Resolution Sample-and-Hold Circuit

作　　者：陈红卫[1] 吴建辉[1] 

机构地区：[1]东南大学电子工程系,江苏南京210096

出　　处：《应用科学学报》2005年第3期274-277,共4页Journal of Applied Sciences

基　　金：国家863计划资助项目(2002AA1Z1230)

摘　　要：提出了一种新型的基于运算放大器的开关电容采样保持电路结构.采用速度补偿解决了高速高分辨采样保持电路对放大器要求增益高和速度快之间的矛盾.具体设计了采样保持电路,特别设计了其中的快速时间连续电压比较器.用Chart0.35μmCMOS工艺,进行HSPICE仿真,结果表明,本文设计的采样保持电路的分辨率为10位,采样速率高于70MHz s.A new sample-and-hold circuit based on an operational amplifier is described in this paper. It is useful to solve the conflict between speed and DC gain of an amplifier in a high-speed and high-resolution sample-and-hold circuit by using a speed compensation circuit. The circuit was simulated by 0.35 μm CMOS technology. The sample rate is higher than 70 MHz per second and the resolution is 10 bits.

关 键 词：采样保持电路 高分辨率 高速 SPICE仿真 CMOS工艺 运算放大器 电压比较器 速度补偿 电路结构 开关电容 采样速率 设计 

分 类 号：TN929.11[电子电信—通信与信息系统] TP274.2[电子电信—信息与通信工程]