高频锁相环的可测性设计  

DFT for High-frequency PLL

作　　者：周红[1] 陈晓东[1] 

机构地区：[1]中科院微电子研究所,北京100029

出　　处：《电子与封装》2005年第8期23-26,共4页Electronics & Packaging

摘　　要：本文针对一款应用于大规模集成电路的CMOS高频锁相环,基于边界扫描技术进行了可测性设计。详细讨论了最高输出频率、输出频率范围和锁定时间参数的测试,给出了详细的测试电路和测试方法,仿真结果表明该方法有效可行。Boundary scan solution of design for testability is proposed based on a CMOS high-speed PLL which is used in VLSI.The test method and circuits are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock.In addition, different simulation results of PLL with and without test circuits are compared.

关 键 词：可测性设计:边界扫描 锁相环 高频 

分 类 号：TN407[电子电信—微电子学与固体电子学]