RS码多路并行译码器的容错设计  

The Fault Tolerant Design or Parallel Decoder for RS Codes

作　　者：龚茂康[1] 谢仲华[1] 蒋璇[1] 

机构地区：[1]扬州大学电子工程系,南京航空航天大学电子工程系

出　　处：《南京航空航天大学学报》1995年第5期662-667,共6页Journal of Nanjing University of Aeronautics & Astronautics

摘　　要：本文根据ＲＳ码的最小重量译码原理，首先提出了一种以最佳配置的移位伴随式实现纠错的并行译码新算法。基于该算法多路并行处理的特点，本文介绍了对实现该算法的核心电路──移位伴随式产生电路进行容错设计的方法，以最少的硬件冗余获得９７％的平均冗余替代率，以此方法研制的译码器，体现了纠错码的信息冗余技术与译码器的硬件容错技术的结合，能有效地提高信息传输的可靠性。According to the principle of minimum weight decoding for Reed-Solomon (RS)codes, it is discussed at first that a new algorithm of parallel decoding can be used to correct errors by an optimum choice of shift syndromes. Based on the characteristics of the parallel process in the algorithm, a method is put forward in which the fault tolerant design for the main circuits, that is the generating circuits of shift syndromes, of a decoder which realizes the algorighm gets a rate of average redundant replacement of 97% with only a least hardware redundance. A hardware decoder emboding the combination of information redundance techniques of error-correcting codes with hardware fault tolerant techniques of decoders can be well used to increase the reliability of information transformation.

关 键 词：译码器 容错技术 可靠性 冗余 

分 类 号：TN919.32[电子电信—通信与信息系统]