可缩放的开路通路地屏蔽电感在片测试结构去嵌入方法  

Scalable Ground-Shielded Open and Thru Fixtures Applied to Inductor De-Embedding

作　　者：菅洪彦[1] 唐珏[1] 唐长文[1] 何捷[1] 闵昊[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《Journal of Semiconductors》2005年第8期1656-1661,共6页半导体学报（英文版）

基　　金：上海市科委(批准号:037062019);上海应用材料基金(批准号:0425)资助项目~~

摘　　要：建立了标准CMOS工艺电感在片测试寄生参量模型.实验验证了相同频率时,信号线寄生的串联电阻、串联电感、并联电容与信号线的长度成正比.进而针对不同外径电感到焊盘之间信号线长度不同,采用相同去嵌入结构引起测量误差,不同的测试去嵌入结构又大大增加芯片面积的问题,首次提出针对该信号线寄生参量的按比例缩放地屏蔽开路通路测试结构去嵌入解决方案.使用0.35μm两层多晶硅、四层互连线的CMOS工艺电感流片验证了该方法的有效性.Parasitical parameters models for a CMOS inductor with two ports were developed. The theory that the parasitical impedance, inductor and capacitance of signal lead between pads and inductor are directly proportional to the length of the signal lead at the same frequency was validated by the tape-out experiments. The inductors with different radii have different lengths of signal leads. The same in-fixture must bring error,but different in-fixtures have too much die area. An improved method for applying hi-directional scaling to on-wafer shield-based open and thru test fixtures is proposed to resolve this problem. This method is reliably validated by the test fixtures that were fabricated on top of a lossy substrate using double-poly four-metal-layer 0. 35μm CMOS technology.

关 键 词：片上电感 按比例缩放 开路通路去嵌入 在片测试 

分 类 号：TM55[电气工程—电器]