一种适合于SoC集成的UART核的设计实现  

Design of a UART IP Core for SoC Application

作　　者：张松[1] 董玲[1] 于宗光[1] 须文波[1] 薛忠杰[1] 

机构地区：[1]江南大学通信与控制工程学院,江苏无锡214036

出　　处：《微电子学与计算机》2005年第9期10-13,共4页Microelectronics & Computer

基　　金：电子元器件可靠性物理及其应用技术国防科技重点实验室基金资助项目(51433020105DZ6801)

摘　　要：文章主要介绍一个通用异步接收器∕发送器(UART)核的设计。按串行通信协议进行设计,具有模块化、兼容性和可配置性,适合于SoC(System-on-a-Chip)应用。仿真结果表明该核满足收发要求,功能正确;在RTL级充分考虑了资源共享,实现了对电路的优化。该IP核已用于一款16位定点DSP芯片的设计中。This paper presents a design of a universal asynchronous receiver and transmitter （UART）. According to the protocol of serial communication, this core has the characteristic of modularity and configurability, and is ideal for system-on-a-chip （SoC） application. The result of the simulation has shown the correctness of the function of the UART core. In the RTL designing, the resource sharing was fully considered and the circuit has been optimized. This IP core has been used in a designing 16-bit fixed-point digital signal processor （DSP） successfully.

关 键 词：异步收发 IP核 VERILOG HDL SoC 串行通信 

分 类 号：TN43[电子电信—微电子学与固体电子学] TP334.7[自动化与计算机技术—计算机系统结构]