10Gb/sNRZ码时钟信息提取电路  

b/s Clock Information Extracting Circuit of NRZ Signal

作　　者：仇应华[1] 王志功[1] 朱恩[1] 冯军[1] 熊明珍[1] 夏春晓[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《固体电子学研究与进展》2005年第3期320-324,共5页Research & Progress of SSE

基　　金：国家863计划项目(2001AA312060)资助

摘　　要：利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。A 10 Gbit/s clock information extracting circuit of NRZ signal is designed and realized by using OMMIC＇s 0.2μm GaAs PHEMT technology. Double balance Gilbert-cell incorporating a capacitively-source-coupled current amplifier and a single-tuned tank as load is utilized to improve the circuit performance. The measured rms jitter of extracted clock signal is 1.18 ps and the peak-to-peck jitter is 8.44 ps with a pseudorandom bit sequences of 22^23- 1 at the bit rate of 9. 953 28 Gb/s. The chip area is 0. 5 mm×1 mm and the DC power consumption is 100 mW under a -5 V supply.

关 键 词：非归零码 时钟信息提取 双平衡Gilbert单元 容性耦合差动电流放大器 砷化镓 

分 类 号：TN36[电子电信—物理电子学]