高频锁相环的可测性设计  

DFT for High-frequency PLL

作　　者：周红[1] 陈晓东[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2005年第8期51-54,共4页Microelectronics & Computer

摘　　要：文章针对一款应用于大规模数字集成电路的CMOS高频锁相环进行了可测性设计,详细讨论了最高输出频率、输出频率范围和锁定时间等参数的测试。分别给出了边界扫描测试和分频器测试两种测试方案,并对两种方案进行了比较,指出了各自的适用范围。对于选用的边界扫描方法,给出了详尽的测试电路图,并进行了电路仿真,仿真结果表明该方法有效可行。In this paper, DFT （Design for Testability） is proposed based on a CMOS high-frequency PLL used in digital VLSI. Two test methods, both test on boundary scan and test-by-divider, are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock. In addition, test circuit for boundary scan is designed and simulated. Simulation results of PLL with and without test circuits are compared, which demonstrates the test method on boundary scan is useful and feasible.

关 键 词：可测性设计 边界扫描 高频 锁相环 

分 类 号：TN407[电子电信—微电子学与固体电子学]