高效复数流水线蝶形单元的FPGA实现  

FPGA Implementation of High Efficiency Pipeline Butterflies

作　　者：朱冰莲[1] 孔杰[1] 

机构地区：[1]重庆大学通信工程学院,重庆400044

出　　处：《电子测量与仪器学报》2005年第4期77-80,共4页Journal of Electronic Measurement and Instrumentation

基　　金：本文工作受重庆市科委应用基础科技项目资助(项目编号:7964)。

摘　　要：在实时信号处理系统的设计中,要求用尽量少的硬件资源实现高速的FFT蝶形运算,本文介绍了一种高效复数流水线蝶形单元的FPGA实现,该方法充分结合信号处理算法和EDA优化手段,从成本和速度两个方面折中考虑,在大大减少存储单元和提高速度的同时,不牺牲额外的硬件成本。其性能对于大点数FFT运算有明显的优势。A real-time signal processing system is requested to realize high speed FFT butterfly computation, and simultaneously, use hardware resource as little as possible. In this paper, we introduce a FPGA implementation of high efficiency complex pipelined butterflies. This application, in a very deep degree, combines signal processing algorithms with the EDA optimizations, and makes a speed-cost tradeoff, which accelerates the calculation speed and decreases the amount of used memory units at the same time. It is proved that this method has an obvious advantage in the computation of big-point FFT.

关 键 词：可编程逻辑器件(FPCA) 快速傅立叶变换(FFT) 流水线蝶形 电子设计自动化(EDA) FPGA实现 蝶形运算 存储单元 流水线 复数 信号处理系统 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论] TN911.72[自动化与计算机技术—计算机科学与技术]