一种用于多通道10 Gbit以太网接口的CMOS3.125 Gb/s接收器(英文)  

A CMOS 3.125 Gb/s Receiver forMultichannel 10 Gbit Ethernet Interface

作　　者：黄林[1] 叶菁华[1] 郭淦[1] 陈一辉[1] 洪志良[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《复旦学报（自然科学版）》2005年第6期941-946,共6页Journal of Fudan University：Natural Science

摘　　要：介绍了一种单片集成的3.125 Gb/s接收器的设计,它适用于IEEE 802.3ae四通道10 Gb/s以太网接口.电路采用了多相时钟结构和并行采样技术以降低电路速度要求.电荷泵采用了常跨导偏置技术以降低环路对工艺、电源电压和温度变化的敏感度.时钟数据恢复电路采用1/5速率时钟降低振荡器的设计难度,时钟恢复的同时完成1:5解串功能,降低了电路功耗.电路采用0.18μm CMOS工艺设计和仿真,总体功耗为95 mW,625 MHz恢复时钟的输出抖动小于75 ps,电路在3.125 Gb/s的数据率和各种工艺角下工作正确.The design of a monolithic integrated 3. 125 Gb/s receiver for IEEE 802.3ae quad channel 10 Gbit Ethernet interface is described. The multiphase clock generator and parallel sampling phase detector are used to reduce the speed requirement. Self-biased constant-gm biasing technique is used for charge-pump phase-locked loop （PLL） to achieve low sensitivity to the variation of environments. The clock and data recovery （CDR） circuit exploits 1/5-rate clock technique to facilitate the design of the ring oscillator and eliminate the need of 1 ： 5 demultiplxer, thereby achieving low power consumption. The circuit has been designed and simulated in 0.18 μm CMOS process. The power dissipation is 95 roW, while the total jitter of recovered clock at 625 MHz is less than 75 ps. The circuit works well at 3. 125 Gb/s data rate and all process comers.

关 键 词：接收器 多相时钟发生器 常跨导偏置 鉴相器 时钟数据恢复 1/5速率时钟 

分 类 号：TN432[电子电信—微电子学与固体电子学]