基于Verilog-A的容栅传感器建模与仿真  

Modeling and Simulation of Capacitive Gate transducer Using Verilog-A

作　　者：杨波[1] 杨银堂[1] 孙龙杰[1] 朱樟明[1] 

机构地区：[1]西安电子科技大学微电子研究所

出　　处：《电子器件》2005年第4期871-874,共4页Chinese Journal of Electron Devices

摘　　要：介绍了容栅传感器结构及其工作原理,并针对容栅传感器应用系统设计验证中所遇到的困难,采用模拟硬件描述语言Verilog-A对其行为进行高层次建模,通过理论推导传感器信号与物理位移的关系和CadenceSpectre仿真器的验证,该模型正确又易于系统验证。The structure and principle of capacitive gate transducer are introduced. For the verification difficulty in its application, capacitive gate transducer is modeled in high level to descript its behavior by analog hard description language Verilog-A. By the theory analysis of the relation between the transducer＇s signal phase and displacement and CadenceSpectre＇s simulation, the mode is proved to be correct and easy to use for system verification.

关 键 词：VERILOG-A SPICE 容栅传感器 动栅 定栅 

分 类 号：TN402[电子电信—微电子学与固体电子学]