CMOS电路中抗Latch-up的保护环结构研究  

Research on Latch-up Guard Ring Issues in CMOS Circuits

作　　者：唐晨[1] 孙伟锋[1] 陆生礼[1] 

机构地区：[1]东南大学国家ASIC系统工程技术研究中心,江苏南京210096

出　　处：《现代电子技术》2006年第4期109-111,共3页Modern Electronics Technique

摘　　要：闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。Latch- up is a parasitic effect in CMOS circuits. Once the PN PN structure is triggered,there will be high current from VDD to GND,which makes the chip invalidation. To the problems during latch - up test, the test method is introduced and the failure process is simulated by Tsuprem4 and Medici. With the two guard rings are analyzed and several structures are simulated,an efficient way of layout design is obtained after triggering voltage and current are compared. The validity is proved by the test results.

关 键 词：寄生双极型晶体管 保护环 闩锁 CMOS集成电路 

分 类 号：TN406[电子电信—微电子学与固体电子学]