高压功率VDMOS管的设计研制  

Study on Power VDMOS of High Voltage

作　　者：王英[1] 何杞鑫[1] 方绍华[1] 

机构地区：[1]浙江大学信电系,杭州310027

出　　处：《电子器件》2006年第1期5-8,共4页Chinese Journal of Electron Devices

摘　　要：随着功率电子器件进一步向高压、高频、大电流方向发展,VDMOS晶体管的市场将会越来越广阔。通过综合各种模型,优化外延层厚度和掺杂浓度,设计了高压VDMOS器件的元胞图形以及器件尺寸,并在终端利用新的思路,从而提高了漏源击穿电压,基于理论分析在工艺上成功实现了耐压为500V,导通电流为3A的功率VDMOS器件。As the electron devices develop towards high voltage,high frequency and high current, VDMOS transistors become more and more important, comprehending kinds of models and optimizing the epitaxial layer, the cell structure and sizes of power VDMOS of high voltage are described and a new approach to improve the breakdown voltage is proposed. Based on the theory VDMOS transistors with 500 V breakdown voltage and 3 A conducting current have been successfully fabricated.

关 键 词：VDMOS 优化外延层 终端保护技术 

分 类 号：TN432[电子电信—微电子学与固体电子学]