低电压低功耗CMOS采样保持电路  

Low-Voltage Low-Power CMOS Sample-and-Hold Circuit

作　　者：郑晓燕[1] 王江[1] 仇玉林[1] 

机构地区：[1]中国科学院微电子学研究所,北京100029

出　　处：《电子器件》2006年第2期318-321,共4页Chinese Journal of Electron Devices

摘　　要：设计了一个用于流水线型模数转换器的低压采样保持电路。为降低采保电路中运放的功耗,本文采用了增益补偿的采样保持电路结构,从而用简单的低增益运放达到高精度的效果,并从运放输出建立时间的角度对其输入电流进行优化。为了提高精度,降低采样开关的电阻并减小非线性误差,设计了信号相关自举电压控制的开关。仿真结果表明在1.8V的电源电压下,达到10bit的精度和50Mbit的采样率,整个采保电路的功耗仅为2.3mW。A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described. Several approaches have been used to reduce the power consumption, including an improved S/H circuit which can be designed using conventional low-gain amplifier and a simple optimum allocation of settling time parameter. To reduce the resistance of sampling switch and nonlinear error, a signal dependent clock bootstrapping system is designed. The simulation results demonstrate that the S/H circuit consumes only 2. 3 mW at 1.8 V supply with an accuracy of 10 bit and a sampling rate of 50 Mbit.

关 键 词：低电压 低功耗 采样保持 

分 类 号：TN402[电子电信—微电子学与固体电子学]