PDP信号存储处理IP核的设计与Verilog HDL实现  

Design of PDP Signal Processing IP Core and Its Implementation Based on Verilog HDL

作　　者：邱崧 胡文静[1,2] 刘锦高[1] 李外云[1] 

机构地区：[1]华东师范大学电子系 [2]湖南理工学院,长沙414006

出　　处：《电子器件》2006年第2期524-527,共4页Chinese Journal of Electron Devices

基　　金：上海市科委AM基金资助(0206)

摘　　要：介绍了等离子显示器的基本电路系统及寻址显示分离子场驱动方法,设计了一种具有伪轮廓消除功能的PDP信号存储处理IP核,作为PDP信号控制系统的核心部分,它具备通用的外部电路接口,有较强的可移植性和可复用性,稍加改动便可应用于不同类型和不同参数的PDP显示控制,缩短了设计周期。利用VerilogHDL语言中有限状态机和参数化设计思想对IP核进行了描述和设计,并在Xi1inx公司的FPGA器件上实现了IP核的功能验证。The controlling system and ADS Sub-fielols driving method of PDP are introduced. As a core in the PDP controlling circuit, PDP signal processing IP Core is designed to have universal circuit interfaces and reduce the false outline. This IP Core which is transplantable and reusable can be readily modified to adapt to different PDP so as to reduce the design cycle. The hardware description of this IP Core is proposed by FSM and Parameterized Designs based on Verilog. The IP core is realized and verified on Xilinx FPGA device.

关 键 词：IP核 交流等离子显示器 伪轮廓Verilog HDL 现场可编程门阵列 有限状态机 

分 类 号：TN915.04[电子电信—通信与信息系统]