高性能通用微处理器体系结构关键技术研究  

Research on High Performance General Purpose Microprocessor Architecture

作　　者：张民选[1] 王永文[1] 邢座程[1] 邓让钰[1] 蒋江[1] 张承义[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机研究与发展》2006年第6期987-992,共6页Journal of Computer Research and Development

基　　金：国家自然科学基金项目(60273069);国家"八六三"高技术研究发展计划基金项目(2002AA110020)~~

摘　　要：X处理器是我国自主设计的基于EPIC思想的高性能通用微处理器·介绍了8级流水线和OLSM执行模型,以很少的硬件代价克服了基本EPIC模型的局限性·设计了一种多分支预测结构,支持多条分支指令的并行执行,并通过判定执行减少分支指令的数目;设计了两级cache存储器,提出DTD低功耗设计方法,并通过前瞻执行隐藏访存的延迟·最后,展望了高性能通用微处理器的发展趋势·The X processor is an EPIC based high-performance general-purpose microprocessor. Eight-stage pipelines and OLSM execution model are designed, which overcomes the limitations of traditional EPIC execution model with little hardware overhead. A multi-branch predication structure is designed for parallel execution of multiple branch instructions. Predication is used to reduce branch instructions. Two-level cache memory is designed. DTD method is presented for low power design and speculation is used to hide memory latency. Finally, the future of high-performance microprocessors is prospected.

关 键 词：微处理器 体系结构 并行 分支 存储器 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]