基于Verilog HDL的高速可综合FSM设计  

Design of high-speed and synthesizable finite state machine based on Verilog HDL

作　　者：王鹏[1] 郭忠文[1] 

机构地区：[1]中国海洋大学计算机科学系,山东青岛266071

出　　处：《计算机工程与设计》2006年第11期2017-2019,2104,共4页Computer Engineering and Design

摘　　要：有限状态机(finitestatemachine,FSM)广泛应用于数字系统的控制器设计中,用Verilog设计的可综合状态机有多种编码风格,通常这些编码风格生成的状态机带有组合逻辑输出。时序分析指出组合逻辑输出型状态机不适合高速系统,提出了一种适合高速系统的寄存器输出型状态机。最后通过实例给出了寄存器输出型状态机的状态编码方法及其可综合Verilog编码风格。FSM （Finite State Machine） is widely used in the controller design of digital system. Synthesizable state machine design using Verilog has many coding styles that normally generate combinational logic outputs. Timing analysis shows that state machine with combinational outputs is not well suited for high-speed system. A state machine with registered output is presented, which is suited for high-speed system. Finally, a method of state encoding for registering the FSM outputs and synthesizable Verilog coding style is provided with an example.

关 键 词：有限状态机 VERILOG HDL 可综合 编码风格 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]