基于BP神经网络的CMOS电路平均功耗宏模型  

Power Macromodel of CMOS Circuits by BP Neural Network

作　　者：墙威[1] 曹阳[1] 鄢媛媛[1] 高洵[1] 

机构地区：[1]武汉大学电子信息学院,湖北武汉430072

出　　处：《武汉大学学报（理学版）》2006年第3期353-356,共4页Journal of Wuhan University:Natural Science Edition

基　　金：国家863计划资助项目(2002AA1Z1490)

摘　　要：提出了一种基于神经网络的功耗宏模型,该模型提取CMOS(互补金属氧化物半导体)集成电路原始输入/输出流的统计特征,采用反向传播BP神经网络对电路的平均功耗建模.与传统的基于查找表和经验方程的宏模型相比,该模型占用内存少,不需要根据不同的电路预先假定拟合函数的形式.基于ISCAS-85电路集的实验结果表明:功耗估计的平均相对误差小于10%,均方根误差可基本控制在5%以下.In this paper we propose a novel back-propagation neural network power macromodeling technique that captures the dependence of power dissipation in CMOS circuits on its primary input signal statistics. Features of the input streams of the circuits are extracted to model average power based on BP neural network. In contrast to previously proposed macromodels, it can be used to do RTL power analysis for any given logic circuit without a large look up table and it dose not require empirically construct specialized analytical equations for the power macromodel. In age absolute relative error of our power macromodel is experiments with the ISCAS-85 circuits, the averbelow 10%. The root-mean-square error is about less than 5% for most circuits.

关 键 词：互补金属氧化物半导体 BP神经网络 功耗宏模型 

分 类 号：TN402[电子电信—微电子学与固体电子学]