一种旨在优化速度的多功能乘累加器设计  

A Speed Optimized Multifunctional MAC Architecture

作　　者：张晓潇[1] 陈杰[1] 韩亮[1] 林川[1] 

机构地区：[1]中国科学院微电子所通信与多媒体SOC实验室,北京100029

出　　处：《科学技术与工程》2006年第13期1917-1920,共4页Science Technology and Engineering

摘　　要：介绍了一种40±16×16位高速乘累加/减器的设计。该乘累加/减单元支持有符号数、无符号数及混合符号数的乘法、乘累加/减运算,并支持多种舍入的乘法、乘累加/减运算。该单元采用了改进的Booth算法和Wallace树结构,简化了部分积的产生,及部分积符号的扩展;优化了Wallace树的连接结构,及后续多个操作数的处理次序,从而显著地提高了乘累加/减器的速度。该设计综合考虑了高性能通用DSP对乘累加/减器的要求,作为某高速高性能定点DSP的一部分,已经实现了RTL电路设计、功能仿真、和PC综合,并准备流片且进行FPGA系统开发板的芯片验证。An algorithm and an afficient architecture for design of a 40 ± 16 × 16 multifunctional multiply-accumulate （MAC） unit are presented, which is optimized for speed and can support signed/unsigned/mixed multiply/multiply-accumulate operations with various rounding and saturating options. Basically, this algorithm is developed on the modified Booth＇ s algorithm and Wallace Tree algorithm by making several improvements to them. It simplifies the generation of the partial products, the signs extension optimizes the connection of the Wallace Tree and the orders of many computing operations. As a result, the parallel MAC unit produced by the proposed algorithm outperforms those not improved in our experiment. These findings have already been implemented as a part of a 16-bit general high performance DSP and now prepared for its tape-out and succeeding verification on FPGA.

关 键 词：高速 乘累加/减器 并行 BOOTH算法 WALLACE树 

分 类 号：TN792[电子电信—电路与系统]