一种基于内插法符号同步电路的设计  

The Design of an Interpolation-based Symbol Timing Synchronization Loop

作　　者：赵行波[1] 张海亮[1] 贺光辉[1] 周祖成[1] 

机构地区：[1]北京清华大学电子工程系

出　　处：《微计算机信息》2006年第11Z期274-276,264,共4页Control & Automation

基　　金：国家"八六三"高技术项目(2002AA1Z1380)资助

摘　　要：提出了一种新的符号同步电路结构,采用立方插值和O&M定时误差检测相结合的算法实现符号定时同步,并通过AlteraDSPBuilder完成该电路的设计、仿真和分析,将设计用AlteraStratixIIFPGA实现,应用在实际的接收机中,证明其能纠正1%的定时误差,工作时钟频率最高可达到130MHz。In this paper, a new structure for symbol synchronizing is proposed. Cubic interpolator and O＆M timing error detector are introduced in this design, and the loop was built with Ahera DSP Builder. After simulation and performance analysis, the design is implemented in Ahera Stratix Ⅱ FPGA. Finally, the application of the design in practical receiver proves it can correct 1% symbol timing error and work at clock rate up to 130MHz.

关 键 词：符号同步 插值 定时误差检测 FPGA 

分 类 号：TN914.4[电子电信—通信与信息系统] TN949.197[电子电信—信息与通信工程]