基于耦合式电平位移结构的高压集成电路  

HVIC with Coupled Level Shift Structure

作　　者：乔明[1] 方健[1] 李肇基[1] 张波[1] 

机构地区：[1]电子科技大学微电子与固体电子学院,成都610054

出　　处：《Journal of Semiconductors》2006年第11期2040-2045,共6页半导体学报（英文版）

基　　金：国家自然科学基金资助项目(批准号:60436030)~~

摘　　要：设计并实现一种耦合式C型(coupled)高压电平位移结构,避免常用S型结构中LDMOS漏极高压互连线(HVI)跨过器件源侧及高压结终端时的两处高场区,以直接耦合式实现了高压电平位移和高低压隔离,且减小了芯片面积.借助Pwell,Nepi,P-sub所形成的JFET效应增加C型结构中隔离电阻;引入金属场板MFP,防止LD-MOS的栅、漏与高压结终端多晶场板短接.利用作者开发的高压SPSM CD工艺,成功研制出基于C型电平位移结构的1000V三相功率MOS栅驱动集成电路.结果表明,C型电平位移结构的最高耐压为1040V,较常用S型结构提高了62.5%,所研制的1000V电路可满足AC220V,AC380V高压领域的需要.A coupled level shift structure is designed and implemented. Compared with conventional S level shift structures, the two high electric fields of an LDMOS and a high voltage junction termination （HVJT） introduced by a high voltage interconnection （HVI） are avoided. The HV level shift and isolation of the high side and low side are directly coupled,so the chip size is reduced. The isolated resistor in the C level shift structure can be increased by a JFET consisting of a Pwell, Nepi, and P-sub, and the short of a poly field plate （PFP） in the LDMOS and HVJT is avoided by use of a metal field plate （MFP）. Using HV single poly single metal （SPSM） CMOS DMOS （CD） technology developed by us,we experiment on a 1000V 3- phase power MOS gate driver circuit with C level shift structure successfully. The experimental results show that the maximal breakdown voltage of the C level shift structure is 1040V, which is 62.5% higher than that of a conventional S structure. The 1000V HVIC can be used for the HV application of AC220V and AC380V.

关 键 词：耦合式 电平位移 高压互连线 高压集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]